VHDL-kieli FPGA-suunnittelussa/Dekooderi
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Lue ensin Digitaalipiirit / Enkooderit ja dekooderit (Encoders-Decoders) |
Dekooderi
[muokkaa | muokkaa wikitekstiä]VHDL toteutus
[muokkaa | muokkaa wikitekstiä]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dekooderi_3_8_EN is
Port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
EN : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end dekooderi_3_8_EN;
architecture Beh of dekooderi_3_8_EN is
begin
D0 <= not A2 and not A1 and not A0 and EN;
D1 <= not A2 and not A1 and A0 and EN;
D2 <= not A2 and A1 and not A0 and EN;
D3 <= not A2 and A1 and A0 and EN;
D4 <= A2 and not A1 and not A0 and EN;
D5 <= A2 and not A1 and A0 and EN;
D6 <= A2 and A1 and not A0 and EN;
D7 <= A2 and A1 and A0 and EN;
end Beh;